`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   12:12:01 05/24/2012
// Design Name:   HexUartPrinter
// Module Name:   /home/azonenberg/native/programming/achd-soc/trunk/hdl/achd-soc/testHexUartPrinter.v
// Project Name:  achd-soc
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: HexUartPrinter
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module testHexUartPrinter;

	// Inputs
	reg clk = 0;
	reg uart_rx = 1;
	reg [7:0] tx_data = 0;
	reg tx_en = 0;
	reg space_en = 0;
	reg newline_en = 0;

	// Outputs
	wire busy;
	wire uart_tx;

	// Instantiate the Unit Under Test (UUT)
	HexUartPrinter uut (
		.clk(clk), 
		.busy(busy), 
		.uart_tx(uart_tx), 
		.uart_rx(uart_rx), 
		.tx_data(tx_data), 
		.tx_en(tx_en), 
		.space_en(space_en), 
		.newline_en(newline_en)
	);

	reg ready = 0;
	initial begin
		#100;
      ready = 1;
	end
	
	always begin
		#6.25;
		clk = ready;
		#6.25;
		clk = 0;
	end
	
	reg[15:0] state = 0;
	always @(posedge clk) begin
	
		space_en <= 0;
		tx_en <= 0;
		tx_data <= 0;
		newline_en <= 0;
	
		case(state)
			0: begin
				tx_data <= 8'h55;
				tx_en <= 1;
				state <= 1;
			end
			
			1: begin
				if(!tx_en && !busy) begin
					space_en <= 1;
					state <= 2;
				end
			end
			
			2: begin
				if(!space_en && !busy) begin
					newline_en <= 1;
					state <= 3;
				end
			end
			
			3: begin
				if(!newline_en && !busy) begin
					tx_data <= 8'h8B;
					tx_en <= 1;
					state <= 4;
				end
			end
			
			4: begin
				if(!tx_en && !busy) begin
					space_en <= 1;
					state <= 5;
				end
			end
			
			5: begin
				if(!space_en && !busy) begin
					tx_data <= 8'hEC;
					tx_en <= 1;
					state <= 6;
				end
			end
			
		endcase
	end
	
      
endmodule

